1. Field of Invention
The present invention relates to a memory accessing and controlling unit. More particularly, the present invention relates to a memory accessing and controlling unit that links a central processing unit (CPU) to a memory cluster. The memory accessing and controlling unit functions in such a way that the CPU can read a sequence of data from the memory without a need to wait for L1 write-back signals to return from the CPU. Hence, time delay due to a memory read operation is reduced.
2. Description of Related Art
Due to the rapid progress in computer technologies, the operating speeds of most computer systems are very fast. Aside from a general increase in the working frequency of a CPU, the efficiency of other associated components inside a computer also increases correspondingly. For example, the accessing rate of a main memory such as dynamic access memory (DRAM) in a computer system has increased. Furthermore, the method of memory control has also improved tremendously. From the earlier version of DRAM control, a fast page mode (FPM) and an extended data out (EDO) mode of operation are developed. Now, the most popular memory control methods is the synchronized DRAM (SDRAM).
FIG. 1 is a block diagram showing a computer system having a conventional memory accessing and controlling unit. The computer system includes a CPU 110, a memory accessing and controlling unit 120 and a memory cluster 130. Through the memory accessing and controlling unit 120, the CPU 110 is able to access the memory cluster 130. One end of the memory accessing and controlling unit 120 has a few signal lines that couple with the CPU 110. Similarly, the other end of the memory accessing and controlling unit 120 has a few signal lines that couple with the memory cluster 130.
The CPU 110 needs to access data in the memory cluster 130 through the memory accessing and controlling unit 120. The unit 120 must be able to receive a data request signal from the CPU 110 and then send appropriate controlling signals to the memory cluster 130. Therefore, the CPU 110 is able to write into or read from the memory cluster 130.
The memory accessing and controlling unit 120 is further divided into a CPU interface circuit 121 and a memory controlling circuit 122. The CPU interface circuit 121 is responsible for processing the signals coming from and transmitting to the CPU 110. When the CPU 110 needs to access the memory cluster 130, a data request signal is sent from the CPU 110 to the CPU interface circuit 121. Next, signals are sent from the CPU interface circuit 121 to the memory controlling circuit 122. Finally, appropriate signals are sent from the memory controlling circuit 122 to the memory cluster 130 for controlling the memory read/write operation. Consequently, data from the CPU 110 can be written into the memory cluster 130 or data can be read back from the memory cluster 130 by the CPU 110.
Signal lines that link the CPU interface circuit 121 with the CPU 110 include ADS, REQ, HITM, HD, HTRDY, DRDY and DBSY. Signal on the ADS line comes from the CPU 110. A low voltage in the ADS line implies that the CPU 110 needs to access data in the memory cluster 130. Signal on the REQ line is also sent by the CPU 110 requesting that data be read from or written to the memory cluster 130. The HITM line is a signal line for the CPU 110 to send out an L1 write-back signal. A low potential at the HITM line implies that the data that need to be read by the CPU 110 have already been changed inside the cache memory 112. Therefore, the changed data need to be written back to the memory cluster 130 first.
Signals DRDY and DBSY are data ready and data busy signals, respectively. Both the DRDY and the DBSY signals are sent by the CPU interface circuit 121 to the CPU 110. When the DRDY and the DBSY lines are both at low potential, it means that data are ready to flow to the CPU 110 through the data lines HD. The signal on the signal line HTRDY is provided by the CPU 110. A positive signal there implies that the data on the data lines HD are sent by the CPU 110.
Signal lines that link the CPU interface circuit 121 with the memory controlling circuit 122 include DADS and DAT. Signal on the signal line DADS is an internal data request signal that reciprocates the signal produced by the ADS signal from the CPU 110. The DAT lines are just data lines.
Signal lines that link the memory controlling circuit 122 with the memory cluster 130 include CMD and MD. Signals on the signal lines CMD are instructions for controlling the memory cluster 130. The MD lines are just data lines used for the transfer of data between the memory cluster 130 and the memory controlling circuit 222.
In general, a CPU sends out a burst of data read requests from time to time. However, if there are any L1 write-back signals, they are not on the signal line HITM until a few clock cycles later. When the CPU sends out an L1 write-back signal, data requested by the CPU must first be written back to the memory cluster. Since the L1 write-back signals are returned a few clock cycles after the issue of the read request signal from the CPU, the conventional controlling unit idles for a few more cycles to be sure that no L1 write-back signals return. Hence, internal data request signals are submitted by the CPU interface circuit a few cycles later, and there is a delay in the return of data to or from the CPU.
Since the conventional memory accessing and controlling unit opt for waiting a few cycles after receiving a data request signal (to be sure that no L1 write-back signal is returned), a few clock cycles are wasted in each request. According to the statistics regarding data transfer between a CPU and its memory in a computer system, data is read by the CPU from memory about 60% of the time. Updated data is written back to the memory from the cache about 15% of the time. In the remaining time, data in the CPU is written to the memory. Consequently, by increasing the processing efficiency of CPU memory read requests, efficiency of the entire computer system may be improved.
In light of the foregoing, there is a need to provide a memory accessing and controlling unit capable of eliminating the wait cycles after the data read request signals are issued, thereby increasing the overall efficiency of a computer system.
Accordingly, the present invention is to provide a memory accessing and controlling unit having a CPU interface circuit and a memory controlling circuit. The CPU interface circuit is capable of sending out an internal data read request signal to the memory controlling circuit for reading data off a memory cluster after a data read request signal is submitted by the CPU, but before the expiration of the pre-defined period for the return of an L1 write-back signal. Hence, the delay resulting from the CPU waiting for the return of an L1 write-back signal is reduced and the overall efficiency of the computer system is improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a memory accessing and controlling unit. The memory accessing and controlling unit is coupled to a CPU and a memory cluster. The CPU accesses data in the memory cluster through the memory accessing and controlling unit. Internally, the memory accessing and controlling unit can be further divided into a CPU interface circuit and a memory controlling circuit. The CPU interface circuit is coupled to the CPU and the memory controlling circuit, and the memory controlling circuit is coupled to the memory cluster.
Operation of the CPU interface circuit is as follows. After the CPU interface circuit receives a data read request signal from the CPU, the CPU interface circuit submits an internal data read request signal to the memory controlling circuit accordingly. Later, when the CPU interface circuit picks up an L1 write-back signal from the CPU, the CPU interface circuit submits a stop signal to the memory controlling circuit.
The memory controlling circuit is a device that picks up the internal data read signal as well as the stop signal submitted by the CPU interface circuit. According to the internal data read signal and the stop signal, the memory controlling circuit operates as follows. First, the required data is retrieved from the memory cluster according to the internal data read request signals. As soon as the memory controlling circuit receives a stop signal, processing of the previous internal data read request is immediately stopped so that the write-back data submitted by the CPU can be written into the memory cluster. If the stop signal arrives after the memory controlling circuit has read-out the data from the memory cluster, the read-out data is discarded. Similarly, the write-back data submitted by the CPU is then written back into the memory cluster.
According to one preferred embodiment of this invention, the CPU sends out an L1 write-back signal after the data read request signal is submitted for a predefined period. In addition, the CPU submits the write-back data after the L1 write-back signal is already out for yet another predefined period. On the other hand, the CPU interface circuit submits a stop signal to the memory controlling circuit in response to the L1 write-back signal only when the memory controlling circuit is transmitting data back to the CPU interface circuit.
According to yet another preferred embodiment of this invention, the memory cluster includes a synchronized dynamic random access memory (SDRAM).
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.